FIGS. 1A to 1F are process views showing a method of fabricating a high voltage CMOS device in the related art.
Referring to FIG. 1A, a pad oxide film 2 is thinly formed on a semiconductor substrate 1 doped with impurity ions. The pad oxide film 2 is typically formed at a thickness of 200 Å to 300 Å.
Referring to FIG. 1B, in order to form a photoresist pattern for forming a high voltage deep well as will be described below, a mask is formed on the pad oxide film 2. Then, a photo align key 3 is formed by etching a portion region of the surface of the semiconductor substrate 1, including the pad oxide film 2, by using the mask.
Referring to FIG. 1C, a photoresist pattern P1 is aligned based on the photo align key 3 and is then formed on the pad oxide film 2.
Referring to FIG. 1D, a high voltage deep well region 4 is formed by doping impurity ions on the substrate using the photoresist pattern P1 as the mask, and then the photoresist pattern P1 is stripped.
Referring to FIG. 1E, an isolation region 5 is formed in a predetermined region of the semiconductor substrate 1 by removing the pad oxide film 2 and performing a LOCOS process.
Referring to FIG. 1F, a logic well region 6 is formed by implanting the impurity ions into the deep well region 4 of the semiconductor substrate 1 in which the isolation region 5 is formed.
A gate oxide film and polysilicon doped with impurity ions are stacked and patterned on the semiconductor substrate 1.
Thereafter, a spacer is formed on the sides of the gate oxide film and the polysilicon by forming an insulating film and performing a blanket etch thereon. The gate oxide film, the polysilicon and the spacer are collectively referred to as a ‘gate structure 7.’
A source and drain region 8 are formed by implanting impurity ions using the gate structure 7 as an implantation mask.
The method of fabricating the high voltage CMOS device in the related art involves the process forming the mask for generating the photo align key on the semiconductor substrate so as to form the photoresist pattern for forming the high voltage deep well region. Since the mask does not perform other functions other than the function of generating the photo align key, other masks should be added. As a result, the process is complicated and manufacturing cost is increased.